Technologies for migrating virtual machines

ABSTRACT

Technologies for migrating virtual machines (VMs) includes a plurality of compute sleds and a memory sled each communicatively coupled to a resource manager server. The resource manager server is configured to identify a compute sled of a for a virtual machine instance, allocate a first set of resources of the identified compute sled for the VM instance, associate a region of memory in a memory pool of a memory sled with the compute sled, and create the VM instance on the compute sled. The resource manager server is further configured to migrate the VM instance to another compute sled, associate the region of memory in the memory pool with the other compute sled, and start-up the VM instance on the other compute sled. Other embodiments are described herein.

CROSS-REFERENCE TO RELATED APPLICATIONS

The present application claims the benefit of U.S. Provisional PatentApplication No. 62/427,268, filed Nov. 29, 2016 and Indian ProvisionalPatent Application No. 201741030632, filed Aug. 30, 2017.

BACKGROUND

Network operators and service providers typically rely on variousnetwork virtualization technologies to manage complex, large-scalecomputing environments, such as high-performance computing (HPC) andcloud computing environments. Typically, these computing environments,or data centers, are comprised of a multitude of network computingdevices (e.g., servers, switches, routers, etc.) which are configured toperform various operations (e.g., process network traffic through thedata center, store data, perform computations, etc.). In order toprovide scalability to meet demand and reduce operational costs, certaindata center operations are typically run inside containers or virtualmachines (VMs) in a virtualized environment of one or more of thenetwork computing devices.

Oftentimes, for various reasons (e.g., data center closures, compromisedserver security, disaster recovery, network infrastructure upgrades,etc.), a container or VM being executed on one network computing deviceneeds to be migrated to another. Although container/VM migration can bea useful tool, the migrations typically require the copying of data(e.g., the container/VM requirements, the workload, the stored dataassociated with the workload, etc.) across the network between thenetwork computing devices. The data copy typically introduces networktraffic, resulting in bandwidth consumption that could otherwise be usedfor other operations.

BRIEF DESCRIPTION OF THE DRAWINGS

The concepts described herein are illustrated by way of example and notby way of limitation in the accompanying figures. For simplicity andclarity of illustration, elements illustrated in the figures are notnecessarily drawn to scale. Where considered appropriate, referencelabels have been repeated among the figures to indicate corresponding oranalogous elements.

FIG. 1 is a simplified diagram of at least one embodiment of a datacenter for executing workloads with disaggregated resources;

FIG. 2 is a simplified diagram of at least one embodiment of a pod ofthe data center of FIG. 1;

FIG. 3 is a perspective view of at least one embodiment of a rack thatmay be included in the pod of FIG. 2;

FIG. 4 is a side plan elevation view of the rack of FIG. 3;

FIG. 5 is a perspective view of the rack of FIG. 3 having a sled mountedtherein;

FIG. 6 is a is a simplified block diagram of at least one embodiment ofa top side of the sled of FIG. 5;

FIG. 7 is a simplified block diagram of at least one embodiment of abottom side of the sled of FIG. 6;

FIG. 8 is a simplified block diagram of at least one embodiment of acompute sled usable in the data center of FIG. 1;

FIG. 9 is a top perspective view of at least one embodiment of thecompute sled of FIG. 8;

FIG. 10 is a simplified block diagram of at least one embodiment of anaccelerator sled usable in the data center of FIG. 1;

FIG. 11 is a top perspective view of at least one embodiment of theaccelerator sled of FIG. 10;

FIG. 12 is a simplified block diagram of at least one embodiment of astorage sled usable in the data center of FIG. 1;

FIG. 13 is a top perspective view of at least one embodiment of thestorage sled of FIG. 12;

FIG. 14 is a simplified block diagram of at least one embodiment of amemory sled usable in the data center of FIG. 1; and

FIG. 15 is a simplified block diagram of a system that may beestablished within the data center of FIG. 1 to execute workloads withmanaged nodes composed of disaggregated resources.

FIG. 16 is a simplified block diagram of at least one embodiment of asystem for migrating virtual machines which includes multiple computesleds, a memory sled, and a resource manager server;

FIG. 17 is a simplified block diagram of at least one embodiment of theresource manager server of the system of FIG. 16;

FIG. 18 is a simplified block diagram of at least one embodiment of oneof the compute sleds of the system of FIG. 16;

FIG. 19 is a simplified block diagram of at least one embodiment of anenvironment that may be established by the resource manager server ofFIGS. 16 and 17;

FIG. 20 is a simplified flow diagram of at least one embodiment of amethod for creating a virtual machine instance that may be performed bythe resource manager server of FIGS. 16, 17, and 19; and

FIG. 21 is a simplified flow diagram of at least one embodiment of amethod for migrating a virtual machine instance that may be performed bythe resource manager server of FIGS. 16, 17, and 19.

DETAILED DESCRIPTION OF THE DRAWINGS

While the concepts of the present disclosure are susceptible to variousmodifications and alternative forms, specific embodiments thereof havebeen shown by way of example in the drawings and will be describedherein in detail. It should be understood, however, that there is nointent to limit the concepts of the present disclosure to the particularforms disclosed, but on the contrary, the intention is to cover allmodifications, equivalents, and alternatives consistent with the presentdisclosure and the appended claims.

References in the specification to “one embodiment,” “an embodiment,”“an illustrative embodiment,” etc., indicate that the embodimentdescribed may include a particular feature, structure, orcharacteristic, but every embodiment may or may not necessarily includethat particular feature, structure, or characteristic. Moreover, suchphrases are not necessarily referring to the same embodiment. Further,when a particular feature, structure, or characteristic is described inconnection with an embodiment, it is submitted that it is within theknowledge of one skilled in the art to effect such feature, structure,or characteristic in connection with other embodiments whether or notexplicitly described. Additionally, it should be appreciated that itemsincluded in a list in the form of “at least one A, B, and C” can mean(A); (B); (C); (A and B); (A and C); (B and C); or (A, B, and C).Similarly, items listed in the form of “at least one of A, B, or C” canmean (A); (B); (C); (A and B); (A and C); (B and C); or (A, B, and C).

The disclosed embodiments may be implemented, in some cases, inhardware, firmware, software, or any combination thereof. The disclosedembodiments may also be implemented as instructions carried by or storedon a transitory or non-transitory machine-readable (e.g.,computer-readable) storage medium, which may be read and executed by oneor more processors. A machine-readable storage medium may be embodied asany storage device, mechanism, or other physical structure for storingor transmitting information in a form readable by a machine (e.g., avolatile or non-volatile memory, a media disc, or other media device).

In the drawings, some structural or method features may be shown inspecific arrangements and/or orderings. However, it should beappreciated that such specific arrangements and/or orderings may not berequired. Rather, in some embodiments, such features may be arranged ina different manner and/or order than shown in the illustrative figures.Additionally, the inclusion of a structural or method feature in aparticular figure is not meant to imply that such feature is required inall embodiments and, in some embodiments, may not be included or may becombined with other features.

Referring now to FIG. 1, a data center 100 in which disaggregatedresources may cooperatively execute one or more workloads (e.g.,applications on behalf of customers) includes multiple pods 110, 120,130, 140, each of which includes one or more rows of racks. As describedin more detail herein, each rack houses multiple sleds, which each maybe embodied as a compute device, such as a server, that is primarilyequipped with a particular type of resource (e.g., memory devices, datastorage devices, accelerator devices, general purpose processors). Inthe illustrative embodiment, the sleds in each pod 110, 120, 130, 140are connected to multiple pod switches (e.g., switches that route datacommunications to and from sleds within the pod). The pod switches, inturn, connect with spine switches 150 that switch communications amongpods (e.g., the pods 110, 120, 130, 140) in the data center 100. In someembodiments, the sleds may be connected with a fabric using IntelOmni-Path technology. As described in more detail herein, resourceswithin sleds in the data center 100 may be allocated to a group(referred to herein as a “managed node”) containing resources from oneor more other sleds to be collectively utilized in the execution of aworkload. The workload can execute as if the resources belonging to themanaged node were located on the same sled. The resources in a managednode may even belong to sleds belonging to different racks, and even todifferent pods 110, 120, 130, 140. Some resources of a single sled maybe allocated to one managed node while other resources of the same sledare allocated to a different managed node (e.g., one processor assignedto one managed node and another processor of the same sled assigned to adifferent managed node). By disaggregating resources to sleds comprisedpredominantly of a single type of resource (e.g., compute sledscomprising primarily compute resources, memory sleds containingprimarily memory resources), and selectively allocating and deallocatingthe disaggregated resources to form a managed node assigned to execute aworkload, the data center 100 provides more efficient resource usageover typical data centers comprised of hyperconverged servers containingcompute, memory, storage and perhaps additional resources). As such, thedata center 100 may provide greater performance (e.g., throughput,operations per second, latency, etc.) than a typical data center thathas the same number of resources.

Referring now to FIG. 2, the pod 110, in the illustrative embodiment,includes a set of rows 200, 210, 220, 230 of racks 240. Each rack 240may house multiple sleds (e.g., sixteen sleds) and provide power anddata connections to the housed sleds, as described in more detailherein. In the illustrative embodiment, the racks in each row 200, 210,220, 230 are connected to multiple pod switches 250, 260. The pod switch250 includes a set of ports 252 to which the sleds of the racks of thepod 110 are connected and another set of ports 254 that connect the pod110 to the spine switches 150 to provide connectivity to other pods inthe data center 100. Similarly, the pod switch 260 includes a set ofports 262 to which the sleds of the racks of the pod 110 are connectedand a set of ports 264 that connect the pod 110 to the spine switches150. As such, the use of the pair of switches 250, 260 provides anamount of redundancy to the pod 110. For example, if either of theswitches 250, 260 fails, the sleds in the pod 110 may still maintaindata communication with the remainder of the data center 100 (e.g.,sleds of other pods) through the other switch 250, 260. Furthermore, inthe illustrative embodiment, the switches 150, 250, 260 may be embodiedas dual-mode optical switches, capable of routing both Ethernet protocolcommunications carrying Internet Protocol (IP) packets andcommunications according to a second, high-performance link-layerprotocol (e.g., Intel's Omni-Path Architecture's, Infiniband) viaoptical signaling media of an optical fabric.

It should be appreciated that each of the other pods 120, 130, 140 (aswell as any additional pods of the data center 100) may be similarlystructured as, and have components similar to, the pod 110 shown in anddescribed in regard to FIG. 2 (e.g., each pod may have rows of rackshousing multiple sleds as described above). Additionally, while two podswitches 250, 260 are shown, it should be understood that in otherembodiments, each pod 110, 120, 130, 140 may be connected to differentnumber of pod switches (e.g., providing even more failover capacity).

Referring now to FIGS. 3-5, each illustrative rack 240 of the datacenter 100 includes two elongated support posts 302, 304, which arearranged vertically. For example, the elongated support posts 302, 304may extend upwardly from a floor of the data center 100 when deployed.The rack 240 also includes one or more horizontal pairs 310 of elongatedsupport arms 312 (identified in FIG. 3 via a dashed ellipse) configuredto support a sled of the data center 100 as discussed below. Oneelongated support arm 312 of the pair of elongated support arms 312extends outwardly from the elongated support post 302 and the otherelongated support arm 312 extends outwardly from the elongated supportpost 304.

In the illustrative embodiments, each sled of the data center 100 isembodied as a chassis-less sled. That is, each sled has a chassis-lesscircuit board substrate on which physical resources (e.g., processors,memory, accelerators, storage, etc.) are mounted as discussed in moredetail below. As such, the rack 240 is configured to receive thechassis-less sleds. For example, each pair 310 of elongated support arms312 defines a sled slot 320 of the rack 240, which is configured toreceive a corresponding chassis-less sled. To do so, each illustrativeelongated support arm 312 includes a circuit board guide 330 configuredto receive the chassis-less circuit board substrate of the sled. Eachcircuit board guide 330 is secured to, or otherwise mounted to, a topside 332 of the corresponding elongated support arm 312. For example, inthe illustrative embodiment, each circuit board guide 330 is mounted ata distal end of the corresponding elongated support arm 312 relative tothe corresponding elongated support post 302, 304. For clarity of theFigures, not every circuit board guide 330 may be referenced in eachFigure.

Each circuit board guide 330 includes an inner wall that defines acircuit board slot 380 configured to receive the chassis-less circuitboard substrate of a sled 400 when the sled 400 is received in thecorresponding sled slot 320 of the rack 240. To do so, as shown in FIG.4, a user (or robot) aligns the chassis-less circuit board substrate ofan illustrative chassis-less sled 400 to a sled slot 320. The user, orrobot, may then slide the chassis-less circuit board substrate forwardinto the sled slot 320 such that each side edge 414 of the chassis-lesscircuit board substrate is received in a corresponding circuit boardslot 380 of the circuit board guides 330 of the pair 310 of elongatedsupport arms 312 that define the corresponding sled slot 320 as shown inFIG. 4. By having robotically accessible and robotically manipulablesleds comprising disaggregated resources, each type of resource can beupgraded independently of each other and at their own optimized refreshrate. Furthermore, the sleds are configured to blindly mate with powerand data communication cables in each rack 240, enhancing their abilityto be quickly removed, upgraded, reinstalled, and/or replaced. As such,in some embodiments, the data center 100 may operate (e.g., executeworkloads, undergo maintenance and/or upgrades, etc.) without humaninvolvement on the data center floor. In other embodiments, a human mayfacilitate one or more maintenance or upgrade operations in the datacenter 100.

It should be appreciated that each circuit board guide 330 is dualsided. That is, each circuit board guide 330 includes an inner wall thatdefines a circuit board slot 380 on each side of the circuit board guide330. In this way, each circuit board guide 330 can support achassis-less circuit board substrate on either side. As such, a singleadditional elongated support post may be added to the rack 240 to turnthe rack 240 into a two-rack solution that can hold twice as many sledslots 320 as shown in FIG. 3. The illustrative rack 240 includes sevenpairs 310 of elongated support arms 312 that define a correspondingseven sled slots 320, each configured to receive and support acorresponding sled 400 as discussed above. Of course, in otherembodiments, the rack 240 may include additional or fewer pairs 310 ofelongated support arms 312 (i.e., additional or fewer sled slots 320).It should be appreciated that because the sled 400 is chassis-less, thesled 400 may have an overall height that is different than typicalservers. As such, in some embodiments, the height of each sled slot 320may be shorter than the height of a typical server (e.g., shorter than asingle rank unit, “1 U”). That is, the vertical distance between eachpair 310 of elongated support arms 312 may be less than a standard rackunit “1 U.” Additionally, due to the relative decrease in height of thesled slots 320, the overall height of the rack 240 in some embodimentsmay be shorter than the height of traditional rack enclosures. Forexample, in some embodiments, each of the elongated support posts 302,304 may have a length of six feet or less. Again, in other embodiments,the rack 240 may have different dimensions. Further, it should beappreciated that the rack 240 does not include any walls, enclosures, orthe like. Rather, the rack 240 is an enclosure-less rack that is openedto the local environment. Of course, in some cases, an end plate may beattached to one of the elongated support posts 302, 304 in thosesituations in which the rack 240 forms an end-of-row rack in the datacenter 100.

In some embodiments, various interconnects may be routed upwardly ordownwardly through the elongated support posts 302, 304. To facilitatesuch routing, each elongated support post 302, 304 includes an innerwall that defines an inner chamber in which the interconnect may belocated. The interconnects routed through the elongated support posts302, 304 may be embodied as any type of interconnects including, but notlimited to, data or communication interconnects to provide communicationconnections to each sled slot 320, power interconnects to provide powerto each sled slot 320, and/or other types of interconnects.

The rack 240, in the illustrative embodiment, includes a supportplatform on which a corresponding optical data connector (not shown) ismounted. Each optical data connector is associated with a correspondingsled slot 320 and is configured to mate with an optical data connectorof a corresponding sled 400 when the sled 400 is received in thecorresponding sled slot 320. In some embodiments, optical connectionsbetween components (e.g., sleds, racks, and switches) in the data center100 are made with a blind mate optical connection. For example, a dooron each cable may prevent dust from contaminating the fiber inside thecable. In the process of connecting to a blind mate optical connectormechanism, the door is pushed open when the end of the cable enters theconnector mechanism. Subsequently, the optical fiber inside the cableenters a gel within the connector mechanism and the optical fiber of onecable comes into contact with the optical fiber of another cable withinthe gel inside the connector mechanism.

The illustrative rack 240 also includes a fan array 370 coupled to thecross-support arms of the rack 240. The fan array 370 includes one ormore rows of cooling fans 372, which are aligned in a horizontal linebetween the elongated support posts 302, 304. In the illustrativeembodiment, the fan array 370 includes a row of cooling fans 372 foreach sled slot 320 of the rack 240. As discussed above, each sled 400does not include any on-board cooling system in the illustrativeembodiment and, as such, the fan array 370 provides cooling for eachsled 400 received in the rack 240. Each rack 240, in the illustrativeembodiment, also includes a power supply associated with each sled slot320. Each power supply is secured to one of the elongated support arms312 of the pair 310 of elongated support arms 312 that define thecorresponding sled slot 320. For example, the rack 240 may include apower supply coupled or secured to each elongated support arm 312extending from the elongated support post 302. Each power supplyincludes a power connector configured to mate with a power connector ofthe sled 400 when the sled 400 is received in the corresponding sledslot 320. In the illustrative embodiment, the sled 400 does not includeany on-board power supply and, as such, the power supplies provided inthe rack 240 supply power to corresponding sleds 400 when mounted to therack 240.

Referring now to FIG. 6, the sled 400, in the illustrative embodiment,is configured to be mounted in a corresponding rack 240 of the datacenter 100 as discussed above. In some embodiments, each sled 400 may beoptimized or otherwise configured for performing particular tasks, suchas compute tasks, acceleration tasks, data storage tasks, etc. Forexample, the sled 400 may be embodied as a compute sled 800 as discussedbelow in regard to FIGS. 8-9, an accelerator sled 1000 as discussedbelow in regard to FIGS. 10-11, a storage sled 1200 as discussed belowin regard to FIGS. 12-13, or as a sled optimized or otherwise configuredto perform other specialized tasks, such as a memory sled 1400,discussed below in regard to FIG. 14.

As discussed above, the illustrative sled 400 includes a chassis-lesscircuit board substrate 602, which supports various physical resources(e.g., electrical components) mounted thereon. It should be appreciatedthat the circuit board substrate 602 is “chassis-less” in that the sled400 does not include a housing or enclosure. Rather, the chassis-lesscircuit board substrate 602 is open to the local environment. Thechassis-less circuit board substrate 602 may be formed from any materialcapable of supporting the various electrical components mounted thereon.For example, in an illustrative embodiment, the chassis-less circuitboard substrate 602 is formed from an FR-4 glass-reinforced epoxylaminate material. Of course, other materials may be used to form thechassis-less circuit board substrate 602 in other embodiments.

As discussed in more detail below, the chassis-less circuit boardsubstrate 602 includes multiple features that improve the thermalcooling characteristics of the various electrical components mounted onthe chassis-less circuit board substrate 602. As discussed, thechassis-less circuit board substrate 602 does not include a housing orenclosure, which may improve the airflow over the electrical componentsof the sled 400 by reducing those structures that may inhibit air flow.For example, because the chassis-less circuit board substrate 602 is notpositioned in an individual housing or enclosure, there is no backplane(e.g., a backplate of the chassis) to the chassis-less circuit boardsubstrate 602, which could inhibit air flow across the electricalcomponents. Additionally, the chassis-less circuit board substrate 602has a geometric shape configured to reduce the length of the airflowpath across the electrical components mounted to the chassis-lesscircuit board substrate 602. For example, the illustrative chassis-lesscircuit board substrate 602 has a width 604 that is greater than a depth606 of the chassis-less circuit board substrate 602. In one particularembodiment, for example, the chassis-less circuit board substrate 602has a width of about 21 inches and a depth of about 9 inches, comparedto a typical server that has a width of about 17 inches and a depth ofabout 39 inches. As such, an airflow path 608 that extends from a frontedge 610 of the chassis-less circuit board substrate 602 toward a rearedge 612 has a shorter distance relative to typical servers, which mayimprove the thermal cooling characteristics of the sled 400.Furthermore, although not illustrated in FIG. 6, the various physicalresources mounted to the chassis-less circuit board substrate 602 aremounted in corresponding locations such that no two substantivelyheat-producing electrical components shadow each other as discussed inmore detail below. That is, no two electrical components, which produceappreciable heat during operation (i.e., greater than a nominal heatsufficient enough to adversely impact the cooling of another electricalcomponent), are mounted to the chassis-less circuit board substrate 602linearly in-line with each other along the direction of the airflow path608 (i.e., along a direction extending from the front edge 610 towardthe rear edge 612 of the chassis-less circuit board substrate 602).

As discussed above, the illustrative sled 400 includes one or morephysical resources 620 mounted to a top side 650 of the chassis-lesscircuit board substrate 602. Although two physical resources 620 areshown in FIG. 6, it should be appreciated that the sled 400 may includeone, two, or more physical resources 620 in other embodiments. Thephysical resources 620 may be embodied as any type of processor,controller, or other compute circuit capable of performing various taskssuch as compute functions and/or controlling the functions of the sled400 depending on, for example, the type or intended functionality of thesled 400. For example, as discussed in more detail below, the physicalresources 620 may be embodied as high-performance processors inembodiments in which the sled 400 is embodied as a compute sled, asaccelerator co-processors or circuits in embodiments in which the sled400 is embodied as an accelerator sled, storage controllers inembodiments in which the sled 400 is embodied as a storage sled, or aset of memory devices in embodiments in which the sled 400 is embodiedas a memory sled.

The sled 400 also includes one or more additional physical resources 630mounted to the top side 650 of the chassis-less circuit board substrate602. In the illustrative embodiment, the additional physical resourcesinclude a network interface controller (NIC) as discussed in more detailbelow. Of course, depending on the type and functionality of the sled400, the physical resources 630 may include additional or otherelectrical components, circuits, and/or devices in other embodiments.

The physical resources 620 are communicatively coupled to the physicalresources 630 via an input/output (I/O) subsystem 622. The I/O subsystem622 may be embodied as circuitry and/or components to facilitateinput/output operations with the physical resources 620, the physicalresources 630, and/or other components of the sled 400. For example, theI/O subsystem 622 may be embodied as, or otherwise include, memorycontroller hubs, input/output control hubs, integrated sensor hubs,firmware devices, communication links (e.g., point-to-point links, buslinks, wires, cables, light guides, printed circuit board traces, etc.),and/or other components and subsystems to facilitate the input/outputoperations. In the illustrative embodiment, the I/O subsystem 622 isembodied as, or otherwise includes, a double data rate 4 (DDR4) data busor a DDR5 data bus.

In some embodiments, the sled 400 may also include aresource-to-resource interconnect 624. The resource-to-resourceinterconnect 624 may be embodied as any type of communicationinterconnect capable of facilitating resource-to-resourcecommunications. In the illustrative embodiment, the resource-to-resourceinterconnect 624 is embodied as a high-speed point-to-point interconnect(e.g., faster than the I/O subsystem 622). For example, theresource-to-resource interconnect 624 may be embodied as a QuickPathInterconnect (QPI), an UltraPath Interconnect (UPI), or other high-speedpoint-to-point interconnect dedicated to resource-to-resourcecommunications.

The sled 400 also includes a power connector 640 configured to mate witha corresponding power connector of the rack 240 when the sled 400 ismounted in the corresponding rack 240. The sled 400 receives power froma power supply of the rack 240 via the power connector 640 to supplypower to the various electrical components of the sled 400. That is, thesled 400 does not include any local power supply (i.e., an on-boardpower supply) to provide power to the electrical components of the sled400. The exclusion of a local or on-board power supply facilitates thereduction in the overall footprint of the chassis-less circuit boardsubstrate 602, which may increase the thermal cooling characteristics ofthe various electrical components mounted on the chassis-less circuitboard substrate 602 as discussed above. In some embodiments, power isprovided to the processors 820 through vias directly under theprocessors 820 (e.g., through the bottom side 750 of the chassis-lesscircuit board substrate 602), providing an increased thermal budget,additional current and/or voltage, and better voltage control overtypical boards.

In some embodiments, the sled 400 may also include mounting features 642configured to mate with a mounting arm, or other structure, of a robotto facilitate the placement of the sled 600 in a rack 240 by the robot.The mounting features 642 may be embodied as any type of physicalstructures that allow the robot to grasp the sled 400 without damagingthe chassis-less circuit board substrate 602 or the electricalcomponents mounted thereto. For example, in some embodiments, themounting features 642 may be embodied as non-conductive pads attached tothe chassis-less circuit board substrate 602. In other embodiments, themounting features may be embodied as brackets, braces, or other similarstructures attached to the chassis-less circuit board substrate 602. Theparticular number, shape, size, and/or make-up of the mounting feature642 may depend on the design of the robot configured to manage the sled400.

Referring now to FIG. 7, in addition to the physical resources 630mounted on the top side 650 of the chassis-less circuit board substrate602, the sled 400 also includes one or more memory devices 720 mountedto a bottom side 750 of the chassis-less circuit board substrate 602.That is, the chassis-less circuit board substrate 602 is embodied as adouble-sided circuit board. The physical resources 620 arecommunicatively coupled to the memory devices 720 via the I/O subsystem622. For example, the physical resources 620 and the memory devices 720may be communicatively coupled by one or more vias extending through thechassis-less circuit board substrate 602. Each physical resource 620 maybe communicatively coupled to a different set of one or more memorydevices 720 in some embodiments. Alternatively, in other embodiments,each physical resource 620 may be communicatively coupled to each memorydevices 720.

The memory devices 720 may be embodied as any type of memory devicecapable of storing data for the physical resources 620 during operationof the sled 400, such as any type of volatile (e.g., dynamic randomaccess memory (DRAM), etc.) or non-volatile memory. Volatile memory maybe a storage medium that requires power to maintain the state of datastored by the medium. Non-limiting examples of volatile memory mayinclude various types of random access memory (RAM), such as dynamicrandom access memory (DRAM) or static random access memory (SRAM). Oneparticular type of DRAM that may be used in a memory module issynchronous dynamic random access memory (SDRAM). In particularembodiments, DRAM of a memory component may comply with a standardpromulgated by JEDEC, such as JESD79F for DDR SDRAM, JESD79-2F for DDR2SDRAM, JESD79-3F for DDR3 SDRAM, JESD79-4A for DDR4 SDRAM, JESD209 forLow Power DDR (LPDDR), JESD209-2 for LPDDR2, JESD209-3 for LPDDR3, andJESD209-4 for LPDDR4 (these standards are available at www.jedec.org).Such standards (and similar standards) may be referred to as DDR-basedstandards and communication interfaces of the storage devices thatimplement such standards may be referred to as DDR-based interfaces.

In one embodiment, the memory device is a block addressable memorydevice, such as those based on NAND or NOR technologies. A memory devicemay also include next-generation nonvolatile devices, such as Intel 3DXPoint™ memory or other byte addressable write-in-place nonvolatilememory devices. In one embodiment, the memory device may be or mayinclude memory devices that use chalcogenide glass, multi-thresholdlevel NAND flash memory, NOR flash memory, single or multi-level PhaseChange Memory (PCM), a resistive memory, nanowire memory, ferroelectrictransistor random access memory (FeTRAM), anti-ferroelectric memory,magnetoresistive random access memory (MRAM) memory that incorporatesmemristor technology, resistive memory including the metal oxide base,the oxygen vacancy base and the conductive bridge Random Access Memory(CB-RAM), or spin transfer torque (STT)-MRAM, a spintronic magneticjunction memory based device, a magnetic tunneling junction (MTJ) baseddevice, a DW (Domain Wall) and SOT (Spin Orbit Transfer) based device, athyristor based memory device, or a combination of any of the above, orother memory. The memory device may refer to the die itself and/or to apackaged memory product. In some embodiments, the memory device maycomprise a transistor-less stackable cross point architecture in whichmemory cells sit at the intersection of word lines and bit lines and areindividually addressable and in which bit storage is based on a changein bulk resistance.

Referring now to FIG. 8, in some embodiments, the sled 400 may beembodied as a compute sled 800. The compute sled 800 is optimized, orotherwise configured, to perform compute tasks. Of course, as discussedabove, the compute sled 800 may rely on other sleds, such asacceleration sleds and/or storage sleds, to perform such compute tasks.The compute sled 800 includes various physical resources (e.g.,electrical components) similar to the physical resources of the sled400, which have been identified in FIG. 8 using the same referencenumbers. The description of such components provided above in regard toFIGS. 6 and 7 applies to the corresponding components of the computesled 800 and is not repeated herein for clarity of the description ofthe compute sled 800.

In the illustrative compute sled 800, the physical resources 620 areembodied as processors 820. Although only two processors 820 are shownin FIG. 8, it should be appreciated that the compute sled 800 mayinclude additional processors 820 in other embodiments. Illustratively,the processors 820 are embodied as high-performance processors 820 andmay be configured to operate at a relatively high power rating. Althoughthe processors 820 generate additional heat operating at power ratingsgreater than typical processors (which operate at around 155-230 W), theenhanced thermal cooling characteristics of the chassis-less circuitboard substrate 602 discussed above facilitate the higher poweroperation. For example, in the illustrative embodiment, the processors820 are configured to operate at a power rating of at least 250 W. Insome embodiments, the processors 820 may be configured to operate at apower rating of at least 350 W.

In some embodiments, the compute sled 800 may also include aprocessor-to-processor interconnect 842. Similar to theresource-to-resource interconnect 624 of the sled 400 discussed above,the processor-to-processor interconnect 842 may be embodied as any typeof communication interconnect capable of facilitatingprocessor-to-processor interconnect 842 communications. In theillustrative embodiment, the processor-to-processor interconnect 842 isembodied as a high-speed point-to-point interconnect (e.g., faster thanthe I/O subsystem 622). For example, the processor-to-processorinterconnect 842 may be embodied as a QuickPath Interconnect (QPI), anUltraPath Interconnect (UPI), or other high-speed point-to-pointinterconnect dedicated to processor-to-processor communications.

The compute sled 800 also includes a communication circuit 830. Theillustrative communication circuit 830 includes a network interfacecontroller (NIC) 832, which may also be referred to as a host fabricinterface (HFI). The NIC 832 may be embodied as, or otherwise include,any type of integrated circuit, discrete circuits, controller chips,chipsets, add-in-boards, daughtercards, network interface cards, otherdevices that may be used by the compute sled 800 to connect with anothercompute device (e.g., with other sleds 400). In some embodiments, theNIC 832 may be embodied as part of a system-on-a-chip (SoC) thatincludes one or more processors, or included on a multichip package thatalso contains one or more processors. In some embodiments, the NIC 832may include a local processor (not shown) and/or a local memory (notshown) that are both local to the NIC 832. In such embodiments, thelocal processor of the NIC 832 may be capable of performing one or moreof the functions of the processors 820. Additionally or alternatively,in such embodiments, the local memory of the NIC 832 may be integratedinto one or more components of the compute sled at the board level,socket level, chip level, and/or other levels.

The communication circuit 830 is communicatively coupled to an opticaldata connector 834. The optical data connector 834 is configured to matewith a corresponding optical data connector of the rack 240 when thecompute sled 800 is mounted in the rack 240. Illustratively, the opticaldata connector 834 includes a plurality of optical fibers which leadfrom a mating surface of the optical data connector 834 to an opticaltransceiver 836. The optical transceiver 836 is configured to convertincoming optical signals from the rack-side optical data connector toelectrical signals and to convert electrical signals to outgoing opticalsignals to the rack-side optical data connector. Although shown asforming part of the optical data connector 834 in the illustrativeembodiment, the optical transceiver 836 may form a portion of thecommunication circuit 830 in other embodiments.

In some embodiments, the compute sled 800 may also include an expansionconnector 840. In such embodiments, the expansion connector 840 isconfigured to mate with a corresponding connector of an expansionchassis-less circuit board substrate to provide additional physicalresources to the compute sled 800. The additional physical resources maybe used, for example, by the processors 820 during operation of thecompute sled 800. The expansion chassis-less circuit board substrate maybe substantially similar to the chassis-less circuit board substrate 602discussed above and may include various electrical components mountedthereto. The particular electrical components mounted to the expansionchassis-less circuit board substrate may depend on the intendedfunctionality of the expansion chassis-less circuit board substrate. Forexample, the expansion chassis-less circuit board substrate may provideadditional compute resources, memory resources, and/or storageresources. As such, the additional physical resources of the expansionchassis-less circuit board substrate may include, but is not limited to,processors, memory devices, storage devices, and/or accelerator circuitsincluding, for example, field programmable gate arrays (FPGA),application-specific integrated circuits (ASICs), securityco-processors, graphics processing units (GPUs), machine learningcircuits, or other specialized processors, controllers, devices, and/orcircuits.

Referring now to FIG. 9, an illustrative embodiment of the compute sled800 is shown. As shown, the processors 820, communication circuit 830,and optical data connector 834 are mounted to the top side 650 of thechassis-less circuit board substrate 602. Any suitable attachment ormounting technology may be used to mount the physical resources of thecompute sled 800 to the chassis-less circuit board substrate 602. Forexample, the various physical resources may be mounted in correspondingsockets (e.g., a processor socket), holders, or brackets. In some cases,some of the electrical components may be directly mounted to thechassis-less circuit board substrate 602 via soldering or similartechniques.

As discussed above, the individual processors 820 and communicationcircuit 830 are mounted to the top side 650 of the chassis-less circuitboard substrate 602 such that no two heat-producing, electricalcomponents shadow each other. In the illustrative embodiment, theprocessors 820 and communication circuit 830 are mounted incorresponding locations on the top side 650 of the chassis-less circuitboard substrate 602 such that no two of those physical resources arelinearly in-line with others along the direction of the airflow path608. It should be appreciated that, although the optical data connector834 is in-line with the communication circuit 830, the optical dataconnector 834 produces no or nominal heat during operation.

The memory devices 720 of the compute sled 800 are mounted to the bottomside 750 of the of the chassis-less circuit board substrate 602 asdiscussed above in regard to the sled 400. Although mounted to thebottom side 750, the memory devices 720 are communicatively coupled tothe processors 820 located on the top side 650 via the I/O subsystem622. Because the chassis-less circuit board substrate 602 is embodied asa double-sided circuit board, the memory devices 720 and the processors820 may be communicatively coupled by one or more vias, connectors, orother mechanisms extending through the chassis-less circuit boardsubstrate 602. Of course, each processor 820 may be communicativelycoupled to a different set of one or more memory devices 720 in someembodiments. Alternatively, in other embodiments, each processor 820 maybe communicatively coupled to each memory device 720. In someembodiments, the memory devices 720 may be mounted to one or more memorymezzanines on the bottom side of the chassis-less circuit boardsubstrate 602 and may interconnect with a corresponding processor 820through a ball-grid array.

Each of the processors 820 includes a heatsink 850 secured thereto. Dueto the mounting of the memory devices 720 to the bottom side 750 of thechassis-less circuit board substrate 602 (as well as the verticalspacing of the sleds 400 in the corresponding rack 240), the top side650 of the chassis-less circuit board substrate 602 includes additional“free” area or space that facilitates the use of heatsinks 850 having alarger size relative to traditional heatsinks used in typical servers.Additionally, due to the improved thermal cooling characteristics of thechassis-less circuit board substrate 602, none of the processorheatsinks 850 include cooling fans attached thereto. That is, each ofthe heatsinks 850 is embodied as a fan-less heatsinks.

Referring now to FIG. 10, in some embodiments, the sled 400 may beembodied as an accelerator sled 1000. The accelerator sled 1000 isoptimized, or otherwise configured, to perform specialized computetasks, such as machine learning, encryption, hashing, or othercomputational-intensive task. In some embodiments, for example, acompute sled 800 may offload tasks to the accelerator sled 1000 duringoperation. The accelerator sled 1000 includes various components similarto components of the sled 400 and/or compute sled 800, which have beenidentified in FIG. 10 using the same reference numbers. The descriptionof such components provided above in regard to FIGS. 6, 7, and 8 applyto the corresponding components of the accelerator sled 1000 and is notrepeated herein for clarity of the description of the accelerator sled1000.

In the illustrative accelerator sled 1000, the physical resources 620are embodied as accelerator circuits 1020. Although only two acceleratorcircuits 1020 are shown in FIG. 10, it should be appreciated that theaccelerator sled 1000 may include additional accelerator circuits 1020in other embodiments. For example, as shown in FIG. 11, the acceleratorsled 1000 may include four accelerator circuits 1020 in someembodiments. The accelerator circuits 1020 may be embodied as any typeof processor, co-processor, compute circuit, or other device capable ofperforming compute or processing operations. For example, theaccelerator circuits 1020 may be embodied as, for example, fieldprogrammable gate arrays (FPGA), application-specific integratedcircuits (ASICs), security co-processors, graphics processing units(GPUs), machine learning circuits, or other specialized processors,controllers, devices, and/or circuits.

In some embodiments, the accelerator sled 1000 may also include anaccelerator-to-accelerator interconnect 1042. Similar to theresource-to-resource interconnect 624 of the sled 600 discussed above,the accelerator-to-accelerator interconnect 1042 may be embodied as anytype of communication interconnect capable of facilitatingaccelerator-to-accelerator communications. In the illustrativeembodiment, the accelerator-to-accelerator interconnect 1042 is embodiedas a high-speed point-to-point interconnect (e.g., faster than the I/Osubsystem 622). For example, the accelerator-to-accelerator interconnect1042 may be embodied as a QuickPath Interconnect (QPI), an UltraPathInterconnect (UPI), or other high-speed point-to-point interconnectdedicated to processor-to-processor communications. In some embodiments,the accelerator circuits 1020 may be daisy-chained with a primaryaccelerator circuit 1020 connected to the NIC 832 and memory 720 throughthe I/O subsystem 622 and a secondary accelerator circuit 1020 connectedto the NIC 832 and memory 720 through a primary accelerator circuit1020.

Referring now to FIG. 11, an illustrative embodiment of the acceleratorsled 1000 is shown. As discussed above, the accelerator circuits 1020,communication circuit 830, and optical data connector 834 are mounted tothe top side 650 of the chassis-less circuit board substrate 602. Again,the individual accelerator circuits 1020 and communication circuit 830are mounted to the top side 650 of the chassis-less circuit boardsubstrate 602 such that no two heat-producing, electrical componentsshadow each other as discussed above. The memory devices 720 of theaccelerator sled 1000 are mounted to the bottom side 750 of the of thechassis-less circuit board substrate 602 as discussed above in regard tothe sled 600. Although mounted to the bottom side 750, the memorydevices 720 are communicatively coupled to the accelerator circuits 1020located on the top side 650 via the I/O subsystem 622 (e.g., throughvias). Further, each of the accelerator circuits 1020 may include aheatsink 1070 that is larger than a traditional heatsink used in aserver. As discussed above with reference to the heatsinks 870, theheatsinks 1070 may be larger than tradition heatsinks because of the“free” area provided by the memory devices 750 being located on thebottom side 750 of the chassis-less circuit board substrate 602 ratherthan on the top side 650.

Referring now to FIG. 12, in some embodiments, the sled 400 may beembodied as a storage sled 1200. The storage sled 1200 is optimized, orotherwise configured, to store data in a data storage 1250 local to thestorage sled 1200. For example, during operation, a compute sled 800 oran accelerator sled 1000 may store and retrieve data from the datastorage 1250 of the storage sled 1200. The storage sled 1200 includesvarious components similar to components of the sled 400 and/or thecompute sled 800, which have been identified in FIG. 12 using the samereference numbers. The description of such components provided above inregard to FIGS. 6, 7, and 8 apply to the corresponding components of thestorage sled 1200 and is not repeated herein for clarity of thedescription of the storage sled 1200.

In the illustrative storage sled 1200, the physical resources 620 areembodied as storage controllers 1220. Although only two storagecontrollers 1220 are shown in FIG. 12, it should be appreciated that thestorage sled 1200 may include additional storage controllers 1220 inother embodiments. The storage controllers 1220 may be embodied as anytype of processor, controller, or control circuit capable of controllingthe storage and retrieval of data into the data storage 1250 based onrequests received via the communication circuit 830. In the illustrativeembodiment, the storage controllers 1220 are embodied as relativelylow-power processors or controllers. For example, in some embodiments,the storage controllers 1220 may be configured to operate at a powerrating of about 75 watts.

In some embodiments, the storage sled 1200 may also include acontroller-to-controller interconnect 1242. Similar to theresource-to-resource interconnect 624 of the sled 400 discussed above,the controller-to-controller interconnect 1242 may be embodied as anytype of communication interconnect capable of facilitatingcontroller-to-controller communications. In the illustrative embodiment,the controller-to-controller interconnect 1242 is embodied as ahigh-speed point-to-point interconnect (e.g., faster than the I/Osubsystem 622). For example, the controller-to-controller interconnect1242 may be embodied as a QuickPath Interconnect (QPI), an UltraPathInterconnect (UPI), or other high-speed point-to-point interconnectdedicated to processor-to-processor communications.

Referring now to FIG. 13, an illustrative embodiment of the storage sled1200 is shown. In the illustrative embodiment, the data storage 1250 isembodied as, or otherwise includes, a storage cage 1252 configured tohouse one or more solid state drives (SSDs) 1254. To do so, the storagecage 1252 includes a number of mounting slots 1256, each of which isconfigured to receive a corresponding solid state drive 1254. Each ofthe mounting slots 1256 includes a number of drive guides 1258 thatcooperate to define an access opening 1260 of the corresponding mountingslot 1256. The storage cage 1252 is secured to the chassis-less circuitboard substrate 602 such that the access openings face away from (i.e.,toward the front of) the chassis-less circuit board substrate 602. Assuch, solid state drives 1254 are accessible while the storage sled 1200is mounted in a corresponding rack 204. For example, a solid state drive1254 may be swapped out of a rack 240 (e.g., via a robot) while thestorage sled 1200 remains mounted in the corresponding rack 240.

The storage cage 1252 illustratively includes sixteen mounting slots1256 and is capable of mounting and storing sixteen solid state drives1254. Of course, the storage cage 1252 may be configured to storeadditional or fewer solid state drives 1254 in other embodiments.Additionally, in the illustrative embodiment, the solid state driversare mounted vertically in the storage cage 1252, but may be mounted inthe storage cage 1252 in a different orientation in other embodiments.Each solid state drive 1254 may be embodied as any type of data storagedevice capable of storing long term data. To do so, the solid statedrives 1254 may include volatile and non-volatile memory devicesdiscussed above.

As shown in FIG. 13, the storage controllers 1220, the communicationcircuit 830, and the optical data connector 834 are illustrativelymounted to the top side 650 of the chassis-less circuit board substrate602. Again, as discussed above, any suitable attachment or mountingtechnology may be used to mount the electrical components of the storagesled 1200 to the chassis-less circuit board substrate 602 including, forexample, sockets (e.g., a processor socket), holders, brackets, solderedconnections, and/or other mounting or securing techniques.

As discussed above, the individual storage controllers 1220 and thecommunication circuit 830 are mounted to the top side 650 of thechassis-less circuit board substrate 602 such that no twoheat-producing, electrical components shadow each other. For example,the storage controllers 1220 and the communication circuit 830 aremounted in corresponding locations on the top side 650 of thechassis-less circuit board substrate 602 such that no two of thoseelectrical components are linearly in-line with other along thedirection of the airflow path 608.

The memory devices 720 of the storage sled 1200 are mounted to thebottom side 750 of the of the chassis-less circuit board substrate 602as discussed above in regard to the sled 400. Although mounted to thebottom side 750, the memory devices 720 are communicatively coupled tothe storage controllers 1220 located on the top side 650 via the I/Osubsystem 622. Again, because the chassis-less circuit board substrate602 is embodied as a double-sided circuit board, the memory devices 720and the storage controllers 1220 may be communicatively coupled by oneor more vias, connectors, or other mechanisms extending through thechassis-less circuit board substrate 602. Each of the storagecontrollers 1220 includes a heatsink 1270 secured thereto. As discussedabove, due to the improved thermal cooling characteristics of thechassis-less circuit board substrate 602 of the storage sled 1200, noneof the heatsinks 1270 include cooling fans attached thereto. That is,each of the heatsinks 1270 is embodied as a fan-less heatsink.

Referring now to FIG. 14, in some embodiments, the sled 400 may beembodied as a memory sled 1400. The storage sled 1400 is optimized, orotherwise configured, to provide other sleds 400 (e.g., compute sleds800, accelerator sleds 1000, etc.) with access to a pool of memory(e.g., in two or more sets 1430, 1432 of memory devices 720) local tothe memory sled 1200. For example, during operation, a compute sled 800or an accelerator sled 1000 may remotely write to and/or read from oneor more of the memory sets 1430, 1432 of the memory sled 1200 using alogical address space that maps to physical addresses in the memory sets1430, 1432. The memory sled 1400 includes various components similar tocomponents of the sled 400 and/or the compute sled 800, which have beenidentified in FIG. 14 using the same reference numbers. The descriptionof such components provided above in regard to FIGS. 6, 7, and 8 applyto the corresponding components of the memory sled 1400 and is notrepeated herein for clarity of the description of the memory sled 1400.

In the illustrative memory sled 1400, the physical resources 620 areembodied as memory controllers 1420. Although only two memorycontrollers 1420 are shown in FIG. 14, it should be appreciated that thememory sled 1400 may include additional memory controllers 1420 in otherembodiments. The memory controllers 1420 may be embodied as any type ofprocessor, controller, or control circuit capable of controlling thewriting and reading of data into the memory sets 1430, 1432 based onrequests received via the communication circuit 830. In the illustrativeembodiment, each storage controller 1220 is connected to a correspondingmemory set 1430, 1432 to write to and read from memory devices 720within the corresponding memory set 1430, 1432 and enforce anypermissions (e.g., read, write, etc.) associated with sled 400 that hassent a request to the memory sled 1400 to perform a memory accessoperation (e.g., read or write).

In some embodiments, the memory sled 1400 may also include acontroller-to-controller interconnect 1442. Similar to theresource-to-resource interconnect 624 of the sled 400 discussed above,the controller-to-controller interconnect 1442 may be embodied as anytype of communication interconnect capable of facilitatingcontroller-to-controller communications. In the illustrative embodiment,the controller-to-controller interconnect 1442 is embodied as ahigh-speed point-to-point interconnect (e.g., faster than the I/Osubsystem 622). For example, the controller-to-controller interconnect1442 may be embodied as a QuickPath Interconnect (QPI), an UltraPathInterconnect (UPI), or other high-speed point-to-point interconnectdedicated to processor-to-processor communications. As such, in someembodiments, a memory controller 1420 may access, through thecontroller-to-controller interconnect 1442, memory that is within thememory set 1432 associated with another memory controller 1420. In someembodiments, a scalable memory controller is made of multiple smallermemory controllers, referred to herein as “chiplets”, on a memory sled(e.g., the memory sled 1400). The chiplets may be interconnected (e.g.,using EMIB (Embedded Multi-Die Interconnect Bridge)). The combinedchiplet memory controller may scale up to a relatively large number ofmemory controllers and I/O ports, (e.g., up to 16 memory channels). Insome embodiments, the memory controllers 1420 may implement a memoryinterleave (e.g., one memory address is mapped to the memory set 1430,the next memory address is mapped to the memory set 1432, and the thirdaddress is mapped to the memory set 1430, etc.). The interleaving may bemanaged within the memory controllers 1420, or from CPU sockets (e.g.,of the compute sled 800) across network links to the memory sets 1430,1432, and may improve the latency associated with performing memoryaccess operations as compared to accessing contiguous memory addressesfrom the same memory device.

Further, in some embodiments, the memory sled 1400 may be connected toone or more other sleds 400 (e.g., in the same rack 240 or an adjacentrack 240) through a waveguide, using the waveguide connector 1480. Inthe illustrative embodiment, the waveguides are 64 millimeter waveguidesthat provide 16 Rx (i.e., receive) lanes and 16 Rt (i.e., transmit)lanes. Each lane, in the illustrative embodiment, is either 16 Ghz or 32Ghz. In other embodiments, the frequencies may be different. Using awaveguide may provide high throughput access to the memory pool (e.g.,the memory sets 1430, 1432) to another sled (e.g., a sled 400 in thesame rack 240 or an adjacent rack 240 as the memory sled 1400) withoutadding to the load on the optical data connector 834.

Referring now to FIG. 15, a system for executing one or more workloads(e.g., applications) may be implemented in accordance with the datacenter 100. In the illustrative embodiment, the system 1510 includes anorchestrator server 1520, which may be embodied as a managed nodecomprising a compute device (e.g., a compute sled 800) executingmanagement software (e.g., a cloud operating environment, such asOpenStack) that is communicatively coupled to multiple sleds 400including a large number of compute sleds 1530 (e.g., each similar tothe compute sled 800), memory sleds 1540 (e.g., each similar to thememory sled 1400), accelerator sleds 1550 (e.g., each similar to thememory sled 1000), and storage sleds 1560 (e.g., each similar to thestorage sled 1200). One or more of the sleds 1530, 1540, 1550, 1560 maybe grouped into a managed node 1570, such as by the orchestrator server1520, to collectively perform a workload (e.g., an application 1532executed in a virtual machine or in a container). The managed node 1570may be embodied as an assembly of physical resources 620, such asprocessors 820, memory resources 720, accelerator circuits 1020, or datastorage 1250, from the same or different sleds 400. Further, the managednode may be established, defined, or “spun up” by the orchestratorserver 1520 at the time a workload is to be assigned to the managed nodeor at any other time, and may exist regardless of whether any workloadsare presently assigned to the managed node. In the illustrativeembodiment, the orchestrator server 1520 may selectively allocate and/ordeallocate physical resources 620 from the sleds 400 and/or add orremove one or more sleds 400 from the managed node 1570 as a function ofquality of service (QoS) targets (e.g., performance targets associatedwith a throughput, latency, instructions per second, etc.) associatedwith a service level agreement for the workload (e.g., the application1532). In doing so, the orchestrator server 1520 may receive telemetrydata indicative of performance conditions (e.g., throughput, latency,instructions per second, etc.) in each sled 400 of the managed node 1570and compare the telemetry data to the quality of service targets todetermine whether the quality of service targets are being satisfied. Ifthe so, the orchestrator server 1520 may additionally determine whetherone or more physical resources may be deallocated from the managed node1570 while still satisfying the QoS targets, thereby freeing up thosephysical resources for use in another managed node (e.g., to execute adifferent workload). Alternatively, if the QoS targets are not presentlysatisfied, the orchestrator server 1520 may determine to dynamicallyallocate additional physical resources to assist in the execution of theworkload (e.g., the application 1532) while the workload is executing

Additionally, in some embodiments, the orchestrator server 1520 mayidentify trends in the resource utilization of the workload (e.g., theapplication 1532), such as by identifying phases of execution (e.g.,time periods in which different operations, each having differentresource utilizations characteristics, are performed) of the workload(e.g., the application 1532) and pre-emptively identifying availableresources in the data center 100 and allocating them to the managed node1570 (e.g., within a predefined time period of the associated phasebeginning). In some embodiments, the orchestrator server 1520 may modelperformance based on various latencies and a distribution scheme toplace workloads among compute sleds and other resources (e.g.,accelerator sleds, memory sleds, storage sleds) in the data center 100.For example, the orchestrator server 1520 may utilize a model thataccounts for the performance of resources on the sleds 400 (e.g., FPGAperformance, memory access latency, etc.) and the performance (e.g.,congestion, latency, bandwidth) of the path through the network to theresource (e.g., FPGA). As such, the orchestrator server 1520 maydetermine which resource(s) should be used with which workloads based onthe total latency associated with each potential resource available inthe data center 100 (e.g., the latency associated with the performanceof the resource itself in addition to the latency associated with thepath through the network between the compute sled executing the workloadand the sled 400 on which the resource is located).

In some embodiments, the orchestrator server 1520 may generate a map ofheat generation in the data center 100 using telemetry data (e.g.,temperatures, fan speeds, etc.) reported from the sleds 400 and allocateresources to managed nodes as a function of the map of heat generationand predicted heat generation associated with different workloads, tomaintain a target temperature and heat distribution in the data center100. Additionally or alternatively, in some embodiments, theorchestrator server 1520 may organize received telemetry data into ahierarchical model that is indicative of a relationship between themanaged nodes (e.g., a spatial relationship such as the physicallocations of the resources of the managed nodes within the data center100 and/or a functional relationship, such as groupings of the managednodes by the customers the managed nodes provide services for, the typesof functions typically performed by the managed nodes, managed nodesthat typically share or exchange workloads among each other, etc.).Based on differences in the physical locations and resources in themanaged nodes, a given workload may exhibit different resourceutilizations (e.g., cause a different internal temperature, use adifferent percentage of processor or memory capacity) across theresources of different managed nodes. The orchestrator server 1520 maydetermine the differences based on the telemetry data stored in thehierarchical model and factor the differences into a prediction offuture resource utilization of a workload if the workload is reassignedfrom one managed node to another managed node, to accurately balanceresource utilization in the data center 100.

To reduce the computational load on the orchestrator server 1520 and thedata transfer load on the network, in some embodiments, the orchestratorserver 1520 may send self-test information to the sleds 400 to enableeach sled 400 to locally (e.g., on the sled 400) determine whethertelemetry data generated by the sled 400 satisfies one or moreconditions (e.g., an available capacity that satisfies a predefinedthreshold, a temperature that satisfies a predefined threshold, etc.).Each sled 400 may then report back a simplified result (e.g., yes or no)to the orchestrator server 1520, which the orchestrator server 1520 mayutilize in determining the allocation of resources to managed nodes.

Referring now to FIG. 16, a system 1600 for migrating virtual machinesmay be implemented in accordance with the data center 100 describedabove with reference to FIG. 1. The illustrative system 1600 includes aresource manager server 1606 communicatively coupled to multiple computesleds 1602 and a memory sled 1608 via a network switch 1604. Theresource manager server 1606 is configured to manage resources of thesystem 1600 to perform various workload operations. The resource managerserver 1606 is additionally configured to manage virtual machines (VMs)to execute a workload (e.g., an application) using the allocatedresources. In some embodiments, one or more containers may be used inconjunction with or independent of a virtual machine (VM) instance.

In use, the resource manager server 1606 receives an indication orotherwise identifies that a VM instance (e.g., the virtual machine 1616)presently being executed on one compute sled 1602 (e.g., compute sled(1) 1602 a) is to be migrated to another compute sled 1602 (e.g.,compute sled (2) 1602 b). Accordingly, as will be described in furtherdetail below, the resource manager server 1606 manages the migration.However, unlike present technologies in which the VM instance 1616 andall associated data would be required to be migrated from the initialcompute sled 1602 a to the other compute sled 1602 b, a previouslyallocated region of memory in a memory pool (e.g., the memory 1612 ofthe memory pool 1614) which was associated with (i.e., mapped to) theinitial compute sled 1602 a is re-mapped to be associated with the othercompute sled 1602 b. As such, the data stored in the memory pool 1614does not need to be transferred across the network fabric at any pointin the migration of the VM, thereby eliminating the bandwidthconsumption associated with the network traffic which would haveotherwise been required to copy the data across the network fabric.

The resource manager server 1606 may be embodied as any type ofcomputing device capable of monitoring and managing resources of thecompute sleds 1602, as well as performing the other functions describedherein. For example, the resource manager server 1606 may be embodied asa computer, a distributed computing system, one or more sleds, a server(e.g., stand-alone, rack-mounted, blade, etc.), a multiprocessor system,a network appliance (e.g., physical or virtual), a desktop computer, aworkstation, a laptop computer, a notebook computer, a processor-basedsystem, or a network appliance. As shown in FIG. 17, the illustrativeresource manager server 1606 includes a compute engine 1702, aninput/output (I/O) subsystem 1708, one or more data storage devices1710, communication circuitry 1712, and one or more peripheral devices1716. It should be appreciated that the resource manager server 1606 mayinclude other or additional components, such as those commonly found ina typical computing device (e.g., various input/output devices and/orother components), in other embodiments. Additionally, in someembodiments, one or more of the illustrative components may beincorporated in, or otherwise form a portion of, another component.

The compute engine 1702 may be embodied as any type of device orcollection of devices capable of performing the various computefunctions as described herein. In some embodiments, the compute engine1702 may be embodied as a single device such as an integrated circuit,an embedded system, a field-programmable-array (FPGA), asystem-on-a-chip (SOC), an application specific integrated circuit(ASIC), reconfigurable hardware or hardware circuitry, or otherspecialized hardware to facilitate performance of the functionsdescribed herein. Additionally, in some embodiments, the compute engine1702 may include, or may be embodied as, a processor 1704 (i.e., acentral processing unit (CPU)) and memory 1706.

The processor 1704 may be embodied as any type of processor capable ofperforming the functions described herein. For example, the processor1704 may be embodied as a single or multi-core processor(s), digitalsignal processor, microcontroller, or other processor orprocessing/controlling circuit. In some embodiments, the processor 1704may be embodied as, include, or otherwise be coupled to a fieldprogrammable gate array (FPGA), an application specific integratedcircuit (ASIC), reconfigurable hardware or hardware circuitry, or otherspecialized hardware to facilitate performance of the functionsdescribed herein.

The memory 1706 may be embodied as any type of volatile (e.g., dynamicrandom access memory (DRAM), etc.) or non-volatile memory or datastorage capable of performing the functions described herein. It shouldbe appreciated that the memory 1706 may include main memory (i.e., aprimary memory) and/or cache memory (i.e., memory that can be accessedmore quickly than the main memory). Volatile memory may be a storagemedium that requires power to maintain the state of data stored by themedium. Non-limiting examples of volatile memory may include varioustypes of random access memory (RAM), such as dynamic random accessmemory (DRAM) or static random access memory (SRAM).

One particular type of DRAM that may be used in a memory module issynchronous dynamic random access memory (SDRAM). In particularembodiments, DRAM of a memory component may comply with a standardpromulgated by JEDEC, such as JESD79F for DDR SDRAM, JESD79-2F for DDR2SDRAM, JESD79-3F for DDR3 SDRAM, JESD79-4A for DDR4 SDRAM, JESD209 forLow Power DDR (LPDDR), JESD209-2 for LPDDR2, JESD209-3 for LPDDR3, andJESD209-4 for LPDDR4 (these standards are available at www.jedec.org).Such standards (and similar standards) may be referred to as DDR-basedstandards and communication interfaces of the storage devices thatimplement such standards may be referred to as DDR-based interfaces.

In one embodiment, the memory device is a block addressable memorydevice, such as those based on NAND or NOR technologies. A memory devicemay also include future generation nonvolatile devices, such as a threedimensional crosspoint memory device (e.g., Intel 3D XPoint™ memory), orother byte addressable write-in-place nonvolatile memory devices. In oneembodiment, the memory device may be or may include memory devices thatuse chalcogenide glass, multi-threshold level NAND flash memory, NORflash memory, single or multi-level Phase Change Memory (PCM), aresistive memory, nanowire memory, ferroelectric transistor randomaccess memory (FeTRAM), anti-ferroelectric memory, magnetoresistiverandom access memory (MRAM) memory that incorporates memristortechnology, resistive memory including the metal oxide base, the oxygenvacancy base and the conductive bridge Random Access Memory (CB-RAM), orspin transfer torque (STT)-MRAM, a spintronic magnetic junction memorybased device, a magnetic tunneling junction (MTJ) based device, a DW(Domain Wall) and SOT (Spin Orbit Transfer) based device, a thyristorbased memory device, or a combination of any of the above, or othermemory. The memory device may refer to the die itself and/or to apackaged memory product.

In some embodiments, 3D crosspoint memory (e.g., Intel 3D XPoint™memory) may comprise a transistor-less stackable cross pointarchitecture in which memory cells sit at the intersection of word linesand bit lines and are individually addressable and in which bit storageis based on a change in bulk resistance. In some embodiments, all or aportion of the memory 1706 may be integrated into the processor 1704. Inoperation, the memory 1706 may store various software and data usedduring operation such as job request data, kernel map data, telemetrydata, applications, programs, libraries, and drivers.

The compute engine 1702 is communicatively coupled to other componentsof the resource manager server 1606 via the I/O subsystem 1708, whichmay be embodied as circuitry and/or components to facilitateinput/output operations with the processor 1704, the memory 1706, andother components of the resource manager server 1606. For example, theI/O subsystem 1708 may be embodied as, or otherwise include, memorycontroller hubs, input/output control hubs, integrated sensor hubs,firmware devices, communication links (e.g., point-to-point links, buslinks, wires, cables, light guides, printed circuit board traces, etc.),and/or other components and subsystems to facilitate the input/outputoperations. In some embodiments, the I/O subsystem 1708 may form aportion of a system-on-a-chip (SoC) and be incorporated, along with oneor more of the processor 1704, the memory 1706, and other components ofthe resource manager server 1606, on a single integrated circuit chip.

The one or more data storage devices 1710 may be embodied as any type ofstorage device(s) configured for short-term or long-term storage ofdata, such as, for example, memory devices and circuits, memory cards,hard disk drives, solid-state drives, or other data storage devices.Each data storage device 1710 may include a system partition that storesdata and firmware code for the data storage device 1710. Each datastorage device 1710 may also include an operating system partition thatstores data files and executables for an operating system.

The communication circuitry 1712 may be embodied as any communicationcircuit, device, or collection thereof, capable of enablingcommunications between the resource manager server 1606 and othercompute devices (e.g., the compute sleds 1602 of FIG. 16) over anetwork. Accordingly, the communication circuitry 1712 may be configuredto use any one or more communication technology (e.g., wired or wirelesscommunications) and associated protocols (e.g., Ethernet, Bluetooth®,Wi-Fi®, WiMAX, etc.) to effect such communication.

The illustrative communication circuitry 1712 includes a networkinterface controller (NIC) 1714, which may also be referred to as a hostfabric interface (HFI). The NIC 1714 may be embodied as one or moreadd-in-boards, daughtercards, network interface cards, controller chips,chipsets, or other devices that may be used by the resource managerserver 1606 to connect with another compute device (e.g., one of thecompute sleds 1602 of FIG. 16). In some embodiments, the NIC 1714 may beembodied as part of a system-on-a-chip (SoC) that includes one or moreprocessors, or included on a multichip package that also contains one ormore processors. In some embodiments, the NIC 1714 may include a localprocessor (not shown) and/or a local memory (not shown) that are bothlocal to the NIC 1714. In such embodiments, the local processor of theNIC 1714 may be capable of performing one or more of the functions ofthe processor 1704 described herein. Additionally or alternatively, insuch embodiments, the local memory of the NIC 1714 may be integratedinto one or more components of the resource manager server 1606 at theboard level, socket level, chip level, and/or other levels.

The one or more peripheral devices 1716 may include any type of devicethat is usable to input information into the resource manager server1606 and/or receive information from the resource manager server 1606.The peripheral devices 1716 may be embodied as any auxiliary deviceusable to input information into the resource manager server 1606, suchas a keyboard, a mouse, a microphone, a barcode reader, an imagescanner, etc., or output information from the resource manager server1606, such as a display, a speaker, graphics circuitry, a printer, aprojector, etc. It should be appreciated that, in some embodiments, oneor more of the peripheral devices 1716 may function as both an inputdevice and an output device (e.g., a touchscreen display, a digitizer ontop of a display screen, etc.). It should be further appreciated thatthe types of peripheral devices 1716 connected to the resource managerserver 1606 may depend on, for example, the type and/or intended use ofthe resource manager server 1606. Additionally or alternatively, in someembodiments, the peripheral devices 1716 may include one or more ports,such as a USB port, for example, for connecting external peripheraldevices to the resource manager server 1606.

Referring back to FIG. 16, the network switch 1604 may be embodied asany type of networking device capable of performing the functionsdescribed herein, including switching network packets between thecompute sleds 1602, the resource manager server 1606, and the memorysled 1608, as well as any other computing devices. For example, thenetwork switch 1604 may be embodied as a top-of-rack switch, amiddle-of-rack switch, or other Ethernet switch. The network switch1604, as described previously, is communicatively coupled to multiplesleds including the compute sleds 1602 and a memory sled 1608.Accordingly, the network switch 1604 is configured to facilitatecommunication between the resource manager server 1606 and the computesleds 1602, and between the resource manager server 1606 and the memorysled 1608, as well as between the compute sleds 1602 and the memory sled1608. While the network switch 1604 is illustratively shown as providingthe communication link between the compute sleds 1602 and the memorysled 1608, it should be appreciated that, in other embodiments, thecompute sleds 1602 and the memory sled 1608 may be connected via a setof dedicated links. In such embodiments, each of the compute sleds 1602may be communicatively coupled to the memory sled 1608 via a dedicatedlink.

The compute sleds 1602 may be embodied as any type of compute devicecapable of performing the functions described herein, includinginstantiating/stopping/starting a VM instance and executing a workload(e.g., within the VM instance). As shown in FIG. 18, an illustrative oneof the compute sleds 1602, has similar components to that of theresource manager server 1606, including a compute engine 1802 with aprocessor 1804 and a memory 1806, an I/O subsystem 1808, communicationcircuitry 1812 with a NIC 1814, and, in some embodiments, one or moredata storage devices 1810 and/or one or more peripheral devices 1816.Accordingly, the similar or like components are not described herein topreserve clarity of the description. In some embodiments, the computesleds 1602 may include other or additional components, such as thosecommonly found in a computing device. Additionally, in some embodiments,one or more of the illustrative components may be incorporated in, orotherwise form a portion of, another component.

Referring again to FIG. 16, the memory sled 1608 may be embodied as anytype of storage device capable of performing the functions describedherein, such as managing a memory pool 1614 of memory 1612 (e.g.,physical storage resources 205-1). To do so, the illustrative memorysled 1608 includes a memory pool controller 1610, which is configured tomanage data into and out of the memory pool 1614 such that the data canbe stored and retrieved by the compute sleds 1602. It should beappreciated that the memory pool controller 1610 may be embodied asvirtual and/or physical hardware, firmware, software, or a combinationthereof. It should be further appreciated that while only a singlememory sled 1608 is shown, other embodiments may include more than onememory sled 1608.

The memory 1612 of the memory pool 1614 may be embodied as any type ofvolatile (e.g., dynamic random access memory (DRAM), etc.) ornon-volatile memory or data storage capable of performing the functionsdescribed herein. Volatile memory may be a storage medium that requirespower to maintain the state of data stored by the medium. Non-limitingexamples of volatile memory may include various types of random accessmemory (RAM), such as dynamic random access memory (DRAM) or staticrandom access memory (SRAM).

One particular type of DRAM that may be used in a memory module issynchronous dynamic random access memory (SDRAM). In particularembodiments, DRAM of a memory component may comply with a standardpromulgated by JEDEC, such as JESD79F for DDR SDRAM, JESD79-2F for DDR2SDRAM, JESD79-3F for DDR3 SDRAM, JESD79-4A for DDR4 SDRAM, JESD209 forLow Power DDR (LPDDR), JESD209-2 for LPDDR2, JESD209-3 for LPDDR3, andJESD209-4 for LPDDR4 (these standards are available at www.jedec.org).Such standards (and similar standards) may be referred to as DDR-basedstandards and communication interfaces of the storage devices thatimplement such standards may be referred to as DDR-based interfaces.

In one embodiment, the memory 1612 may be embodied as a blockaddressable memory device, such as those based on NAND or NORtechnologies. A memory device may also include future generationnonvolatile devices, such as a three dimensional (3D) crosspoint memorydevice (e.g., Intel 3D XPoint™ memory), or other byte addressablewrite-in-place nonvolatile memory devices. In such embodiments, the 3Dcrosspoint memory (e.g., Intel 3D XPoint™ memory) may comprise atransistor-less stackable cross point architecture in which memory cellssit at the intersection of word lines and bit lines and are individuallyaddressable and in which bit storage is based on a change in bulkresistance.

In another embodiment, the memory 1612 may be or may include memorydevices that use chalcogenide glass, multi-threshold level NAND flashmemory, NOR flash memory, single or multi-level Phase Change Memory(PCM), a resistive memory, nanowire memory, ferroelectric transistorrandom access memory (FeTRAM), anti-ferroelectric memory,magnetoresistive random access memory (MRAM) memory that incorporatesmemristor technology, resistive memory including the metal oxide base,the oxygen vacancy base and the conductive bridge Random Access Memory(CB-RAM), or spin transfer torque (STT)-MRAM, a spintronic magneticjunction memory based device, a magnetic tunneling junction (MTJ) baseddevice, a DW (Domain Wall) and SOT (Spin Orbit Transfer) based device, athyristor based memory device, or a combination of any of the above, orother memory. The memory device may refer to the die itself and/or to apackaged memory product.

The illustrative compute sleds 1602 include a first compute sled,designated as compute sled (1) 1602 a, a second compute sled, designatedas compute sled (2) 1602 b, and a third compute sled, designated ascompute sled (N) 1602 c (e.g., in which the compute sled (N) 1602 crepresents the “Nth” compute sled 1602, wherein “N” is a positiveinteger). It should be appreciated that, in some embodiments, one ormore of the compute sleds 1602 may be grouped into a managed node, suchas by the resource manager server 1606, to collectively perform aworkload, such as an application. A managed node may be embodied as anassembly of resources, such as compute resources, memory resources,storage resource, or other resources, from the same or different sledsor racks.

Further, a managed node may be established, defined, or “spun up” by theresource manager server 1606 at the time a workload is to be assigned tothe managed node or at any other time, and may exist regardless ofwhether any workloads are presently assigned to the managed node. Theresource manager server 1606 may, in some embodiments, perform one ormore orchestration operations in support of a cloud operatingenvironment, such as OpenStack, and managed nodes established by theresource manager server 1606 may execute one or more applications orprocesses (i.e., workloads), such as in the VMs or containers, on behalfof a user of a client device (not shown) communicatively coupled to theresource manager server 1606 (e.g., via a network).

Referring now to FIG. 19, the resource manager server 1606 may establishan environment 1900 during operation. The illustrative environment 1900includes a network connection manager 1910, a memory pool communicator1920, a resource allocator 1930, and a VM instance manager 1940. Each ofthe components of the environment 1900 may be embodied as hardware,firmware, software, or a combination thereof. As such, in someembodiments, one or more of the components of the environment 1900 maybe embodied as circuitry or a collection of electrical devices (e.g.,network connection management circuitry 1910, memory pool communicationcircuitry 1920, resource allocation circuitry 1930, VM instancemanagement circuitry 1940, etc.). It should be appreciated that, in suchembodiments, one or more of the network connection management circuitry1910, the memory pool communication circuitry 1920, the resourceallocation circuitry 1930, and the VM instance management circuitry 1940may form a portion of one or more of the compute engine 1702, the one ormore data storage devices 1710, the communication circuitry 1712, and/orany other components of the resource manager server 1606.

In the illustrative embodiment, the environment 1900 additionallyincludes resource data 1902 and virtual machine data 1904, each of whichmay be embodied as any data established by the resource manager server1606. The resource data 1902 may include any data usable to identifyand/or allocate resources of the compute sleds 1602 and/or the memorysled 1608. The virtual machine data 1904 may include any data usable toidentify VM instances (e.g., the VM instance 1616 of FIG. 16) and therespective compute sleds 1602 on which the VM instances are presentlybeing executed. The virtual machine data 1904 may additionally includeVM resource requirement data usable to identify what resources arerequired for each VM instance.

The network connection manager 1910, which may be embodied as hardware,firmware, software, virtualized hardware, emulated architecture, and/ora combination thereof as discussed above, is configured to facilitateinbound and outbound network communications (e.g., network traffic,network packets, network flows, etc.) to and from the resource managerserver 1606, respectively. To do so, the network connection manager 1910is configured to receive and process data packets from one system orcomputing device (e.g., one of the compute sleds 1602) and to prepareand send data packets to another computing device or system (e.g., oneof the compute sleds 1602). Accordingly, in some embodiments, at least aportion of the functionality of the network connection manager 1910 maybe performed by the communication circuitry 1712, or more particularlyby the NIC 1714.

The memory pool communicator 1920, which may be embodied as hardware,firmware, software, virtualized hardware, emulated architecture, and/ora combination thereof as discussed above, is configured to facilitatetransmissions between the resource manager server 1606 and a memory poolcontroller of a memory pool (e.g., the memory pool controller 1610 ofthe memory pool 1614 of FIG. 16). For example, the memory poolcommunicator 1920 is configured to generate and transmit memoryallocation and memory map requests to the memory pool controller 1610which are usable to allocate regions of memory (i.e., in response to areceived memory allocation request) and map allocated regions of memoryto a particular compute sled 1602 (i.e., in response to a receivedmemory map request).

The resource allocator 1930, which may be embodied as hardware,firmware, software, virtualized hardware, emulated architecture, and/ora combination thereof as discussed above, is configured to manage theavailable and allocated resources of the compute sleds 1602. To do so,the resource allocator 1930 may be configured to identify dataassociated with the resources, such as a compute capacity/availability,a memory bandwidth capacity/availability, a data storagecapacity/availability, and/or a level of reliability, resiliency, and/oravailability of the resources. In some embodiments, the resourceallocator 1930 may be configured to store data related to the presentlyand/or historically available and/or allocated resources in the resourcedata 1902.

The VM instance manager 1940, which may be embodied as hardware,firmware, software, virtualized hardware, emulated architecture, and/ora combination thereof as discussed above, is configured to manage thecreation, migration, and deletion of VM instances on the compute sleds1602. To do so, the illustrative VM instance manager 1940 includes aresource identifier 1942 and a migration manager 1944. The resourceidentifier 1942 is configured to identify which resources to allocatefor a particular purpose (e.g., a workload). Such resources may beallocated by type, amount, performance, intended use, etc., and mayinclude network communication resources, storage resources, computeresources, etc.

The migration manager 1944 is configured to detect whether a migrationtrigger has been detected. To do so, for example, the migration manager1944 may be configured to collect or otherwise analyze collectedtelemetry data to determine whether certain conditions exist such that amigration of a VM from one compute sled 1602 to another compute sled1602, or more particularly from a CPU on a compute sled 1602 (e.g., theprocessor 1804 of the illustrative compute sled 1602 of FIG. 18) to adifferent CPU on another compute sled 1602, is required.

Additionally, the migration manager 1944 is configured to manage themigration of a VM instance in response to having detected a migrationtriggering event. To do so, the migration manager 1944 may be configuredto identify the compute sled 1602 on which the VM instance to bemigrated is presently being executed and transmit an indication to theidentified compute sled 1602 that indicates which VM instance is to bemigrated. Accordingly, upon receipt, the compute sled 1602 can stop theVM instance and initiate a data flush to a mapped region of memory in amemory pool (e.g., the memory 1612 in the memory pool 1614 of FIG. 16).The migration manager 1944 is further configured to migrate theworkload/VM instance to the new compute sled 1602 and initiate there-mapping of the region of memory to the new compute sled 1602 and thestartup of the VM instance on the new compute sled 1602. To initiate there-mapping of the region of memory to the new compute sled 1602, themigration manager 1944 is configured to provide identifying informationof the old and new compute sleds 1602 to the memory pool controller 1610(e.g., via the memory pool communicator 1920) which is usable by thememory pool controller 1610 to change the mapping of the data associatedwith the migrated VM instance from the old compute sled 1602 to the newcompute sled 1602. While the illustrative embodiment described herein isreferring to a VM instance, it should be appreciated that the migrationoperations described herein may be performed on another object, such asa container, in other embodiments.

Referring now to FIG. 20, in use, a resource manager server (e.g.,resource manager server 1606 of FIG. 16) may execute a method 2000 forcreating a VM instance (e.g., the VM instance 1616 of FIG. 16) on acompute sled (e.g., one of the compute sleds 1602), or more particularlyon a CPU of the compute sled 1602. The method 2000 begins in block 2002,in which the resource manager server 1606 determines whether to create aVM instance 1616. If so, the method 2000 advances to block 2004, inwhich the resource manager server 1606 determines which resources (e.g.,compute resources, storage resources, network resources, etc.) arerequired by a workload to be processed by or otherwise run on the VMinstance 1616.

In block 2006, the resource manager server 1606 determines a computesled 1602 (e.g., one of the compute sled (1) 1602 a, the compute sled(2) 1602 b, the compute sled (N) 1602 c of FIG. 16) on which to launchthe VM instance 1616. To do so, in block 2008, the resource managerserver 1606 first identifies the available resources of each availablecompute sled 1602. Additionally, in block 2010, the resource managerserver 1606 determines the compute sled to launch the VM instance 1616based on the determined resources required by the workload and theidentified available resources of each available compute sled 1602.

In block 2012, the resource manager server 1606 allocates resources ofthe determined compute sled for use by the VM instance. In block 2014,the resource manager server 1606 allocates a region of memory in amemory pool (e.g., the memory 1612 in the memory pool 1614 of FIG. 16)to be associated with the compute sled 1602. It should be appreciatedthat the regions of memory may be private (i.e., dedicated to thecompute sled 1602) or shared among more than one compute sled 1602. Todo so, in block 2016, the resource manager server 1606 transmits amemory allocation request to a memory pool controller (e.g., the memorypool controller 1610) of the memory pool 1614. Additionally, in block2018, the resource manager server 1606 includes information usable tomap the compute sled to the allocated memory region (e.g., identifyinginformation of the compute sled 1602 and/or the CPU of the compute sled1602 on which the VM instance is to be run). In block 2020, the resourcemanager server 1606 creates the VM instance 1616.

Referring now to FIG. 21, in use, a resource manager server 1606 (e.g.,resource manager server 1606 of FIG. 16) may execute a method 2100 formigrating an existing VM instance (e.g., the VM instance 1616 of FIG.16) from one compute sled 1602 (e.g., the compute sled (1) 1602 a) toanother compute sled 1602 (e.g., the compute sled (2) 1602 b), or moreparticularly from one CPU (e.g., the processor 1804 of the illustrativecompute sled 1602 of FIG. 18) of a compute sled 1602 to a CPU of anothercompute sled 1602. The method 2100 begins in block 2102, in which theresource manager server 1606 determines whether to migrate a VM instance1616. If so, the method 2100 advances to block 2104, in which theresource manager server 1606 retrieves the resources (e.g., computeresources, storage resources, network resources, etc.) which havepreviously been determined as being required by the workload beingprocessed by or otherwise run on the VM instance 1616.

In block 2106, the resource manager server 1606 determines anothercompute sled 1602 on which to migrate the VM instance 1616 to. To do so,in block 2108, the resource manager server 1606 first identifies theavailable resources of each of the other available compute sleds 1602.Additionally, in block 2110, the resource manager server 1606 determinesthe compute sled to migrate the VM instance 1616 to based on theretrieved resources required by the workload and the identifiedavailable resources of each of the other available compute sleds 1602.

In block 2112, the resource manager server 1606 allocates resources ofthe determined other compute sled for use by the VM instance 1616 uponbeing migrated. In block 2114, the resource manager server 1606 migratesthe VM instance 1616 to the other determined compute sled 1602. In otherwords, the data (e.g., software/hardware thread states) associated withthe workload being processed by the VM instance 1616 and/or datacorresponding to the VM instance 1616 itself are migrated to the othercompute sled 1602. In block 2116, the resource manager server 1606re-maps the region of memory in the memory pool from the previouslyassociated compute sled 1602 (i.e., from which the VM instance 1616 isbeing migrated from) to the other compute sled 1602 (i.e., to which theVM instance 1616 is being migrated to). To do so, in block 2118, theresource manager server 1606 transmits a memory re-map request to amemory pool controller (e.g., the memory pool controller 1610) of thememory pool 1614. Additionally, in block 2120, the resource managerserver 1606 includes information usable to re-map the allocated memoryregion from the previously associated compute sled 1602 to the computesled 1602 which the VM instance 1616 is being migrated to. In block2122, the resource manager server 1606 starts-up the VM instance 1616 onthe other compute sled 1602.

EXAMPLES

Illustrative examples of the technologies disclosed herein are providedbelow. An embodiment of the technologies may include any one or more,and any combination of, the examples described below.

Example 1 includes a resource manager server for migrating virtualmachines, the resource manager server comprising a compute engine toidentify a compute sled of a plurality of compute sleds for a virtualmachine (VM) instance, wherein each of the compute sleds iscommunicatively coupled to the resource manager server; allocate a firstset of resources of the identified compute sled for the VM instance;associate a region of memory in a memory pool of a memory sled with thecompute sled, wherein the memory sled is communicatively coupled to theresource manager server; create the VM instance on the compute sled;allocate, in response to determined determination that the VM instanceis to be migrated, a second set of resources of another compute sled ofthe plurality of compute sleds for the VM instance; migrate the VMinstance to the other compute sled; associate the region of memory inthe memory pool with the other compute sled; and start-up the VMinstance on the other compute sled.

Example 2 includes the subject matter of Example 1, and wherein toallocate the first set of resources of the compute sled comprises to (i)determine a set of resources required by a workload to be processed bythe VM instance and (ii) allocate the first set of resources of thecompute sled as a function of the determined required set of resources.

Example 3 includes the subject matter of any of Examples 1 and 2, andwherein to allocate the first set of resources of the compute sledfurther comprises to (i) identify available resources of each of theplurality of compute sleds and (ii) allocate the first set of resourcesof the compute sled as a function of the identified available resources.

Example 4 includes the subject matter of any of Examples 1-3, andwherein to associate the region of memory in the memory pool of thememory sled with the compute sled comprises to transmit a memoryallocation request to a memory pool controller of the memory pool thatis usable to allocate the region of memory and map the allocated regionof memory to the compute sled.

Example 5 includes the subject matter of any of Examples 1-4, andwherein to migrate the VM instance to the other compute sled comprisesto transmit one or more threads associated with the workload associatedwith the VM instance to the other compute sled.

Example 6 includes the subject matter of any of Examples 1-5, andwherein to associate the region of memory in the memory pool of thememory sled with the other compute sled comprises to transmit a memoryallocation request to a memory pool controller of the memory pool thatis usable to map the allocated region of memory to the other computesled.

Example 7 includes the subject matter of any of Examples 1-6, andwherein to allocate the second set of resources of the compute sledcomprises to (i) retrieve a set of resources required by a workloadbeing processed by the VM instance and (ii) allocate the second set ofresources of the compute sled as a function of the retrieved requiredset of resources.

Example 8 includes the subject matter of any of Examples 1-7, andwherein to allocate the second set of resources of the other computesled further comprises to (i) identify available resources of each ofthe plurality of compute sleds and (ii) allocate the second set ofresources of the other compute sled as a function of the identifiedavailable resources.

Example 9 includes a method for migrating virtual machines, thecomprising identifying, by a compute engine of a resource managerserver, a compute sled of a plurality of compute sleds for a virtualmachine (VM) instance, wherein each of the compute sleds iscommunicatively coupled to the resource manager server; allocating, bythe compute engine, a first set of resources of the identified computesled for the VM instance; associating, by the compute engine, a regionof memory in a memory pool of a memory sled with the compute sled,wherein the memory sled is communicatively coupled to the resourcemanager server; creating, by the compute engine, the VM instance on thecompute sled; allocating, by the compute engine and in response todetermined determination that the VM instance is to be migrated, asecond set of resources of another compute sled of the plurality ofcompute sleds for the VM instance; migrating, by the compute engine, theVM instance to the other compute sled; associating, by the computeengine, the region of memory in the memory pool with the other computesled; and starting-up, by the compute engine, the VM instance on theother compute sled.

Example 10 includes the subject matter of Example 9, and whereinallocating the first set of resources of the compute sled comprisesdetermining a set of resources required by a workload to be processed bythe VM instance; and allocating the first set of resources of thecompute sled as a function of the determined required set of resources.

Example 11 includes the subject matter of any of Examples 9 and 10, andwherein allocating the first set of resources of the compute sledfurther comprises identifying available resources of each of theplurality of compute sleds; and allocating the first set of resources ofthe compute sled as a function of the identified available resources.

Example 12 includes the subject matter of any of Examples 9-11, andwherein associating the region of memory in the memory pool of thememory sled with the compute sled comprises transmitting a memoryallocation request to a memory pool controller of the memory pool thatis usable to allocate the region of memory and map the allocated regionof memory to the compute sled.

Example 13 includes the subject matter of any of Examples 9-12, andwherein migrating the VM instance to the other compute sled comprisestransmitting one or more threads associated with the workload associatedwith the VM instance to the other compute sled.

Example 14 includes the subject matter of any of Examples 9-13, andwherein associating the region of memory in the memory pool of thememory sled with the other compute sled comprises transmitting a memoryallocation request to a memory pool controller of the memory pool thatis usable to map the allocated region of memory to the other computesled.

Example 15 includes the subject matter of any of Examples 9-14, andwherein allocating the second set of resources of the compute sledcomprises retrieving a set of resources required by a workload beingprocessed by the VM instance; and allocating the second set of resourcesof the compute sled as a function of the retrieved required set ofresources.

Example 16 includes the subject matter of any of Examples 9-15, andwherein allocating the second set of resources of the other compute sledfurther comprises identifying available resources of each of theplurality of compute sleds; and allocating the second set of resourcesof the other compute sled as a function of the identified availableresources.

Example 17 includes one or more machine-readable storage mediacomprising a plurality of instructions stored thereon that, in responseto being executed, cause a resource manager server to perform the methodof any of Examples 9-16.

Example 18 includes a resource manager server for improving throughputin a network, the resource manager server comprising one or moreprocessors; one or more memory devices having stored therein a pluralityof instructions that, when executed by the one or more processors, causethe resource manager server to perform the method of any of Examples9-16.

Example 19 includes a resource manager server for migrating virtualmachines, the resource manager server comprising virtual machineinstance management circuitry to identify a compute sled of a pluralityof compute sleds for a virtual machine (VM) instance, wherein each ofthe compute sleds is communicatively coupled to the resource managerserver; allocate a first set of resources of the identified compute sledfor the VM instance; associate a region of memory in a memory pool of amemory sled with the compute sled, wherein the memory sled iscommunicatively coupled to the resource manager server; create the VMinstance on the compute sled; allocate, in response to determineddetermination that the VM instance is to be migrated, a second set ofresources of another compute sled of the plurality of compute sleds forthe VM instance; migrate the VM instance to the other compute sled;associate the region of memory in the memory pool with the other computesled; and start-up the VM instance on the other compute sled.

Example 20 includes the subject matter of Example 19, and wherein toallocate the first set of resources of the compute sled comprises to (i)determine a set of resources required by a workload to be processed bythe VM instance and (ii) allocate the first set of resources of thecompute sled as a function of the determined required set of resources.

Example 21 includes the subject matter of any of Examples 19 and 20, andwherein to allocate the first set of resources of the compute sledfurther comprises to (i) identify available resources of each of theplurality of compute sleds and (ii) allocate the first set of resourcesof the compute sled as a function of the identified available resources.

Example 22 includes the subject matter of any of Examples 19-21, andwherein to associate the region of memory in the memory pool of thememory sled with the compute sled comprises to transmit a memoryallocation request to a memory pool controller of the memory pool thatis usable to allocate the region of memory and map the allocated regionof memory to the compute sled.

Example 23 includes the subject matter of any of Examples 19-22, andwherein to migrate the VM instance to the other compute sled comprisesto transmit one or more threads associated with the workload associatedwith the VM instance to the other compute sled.

Example 24 includes the subject matter of any of Examples 19-23, andwherein to associate the region of memory in the memory pool of thememory sled with the other compute sled comprises to transmit a memoryallocation request to a memory pool controller of the memory pool thatis usable to map the allocated region of memory to the other computesled.

Example 25 includes the subject matter of any of Examples 19-24, andwherein to allocate the second set of resources of the compute sledcomprises to (i) retrieve a set of resources required by a workloadbeing processed by the VM instance and (ii) allocate the second set ofresources of the compute sled as a function of the retrieved requiredset of resources.

Example 26 includes the subject matter of any of Examples 19-25, andwherein to allocate the second set of resources of the other computesled further comprises to (i) identify available resources of each ofthe plurality of compute sleds and (ii) allocate the second set ofresources of the other compute sled as a function of the identifiedavailable resources.

Example 27 includes a resource manager server for migrating virtualmachines, the resource manager server comprising circuitry foridentifying, by a compute engine of the resource manager server, acompute sled of a plurality of compute sleds for a virtual machine (VM)instance, wherein each of the compute sleds is communicatively coupledto the resource manager server; circuitry for allocating, by the computeengine, a first set of resources of the identified compute sled for theVM instance; means for associating, by the compute engine, a region ofmemory in a memory pool of a memory sled with the compute sled, whereinthe memory sled is communicatively coupled to the resource managerserver; circuitry for creating, by the compute engine, the VM instanceon the compute sled; circuitry for allocating, by the compute engine andin response to determined determination that the VM instance is to bemigrated, a second set of resources of another compute sled of theplurality of compute sleds for the VM instance; circuitry for migrating,by the compute engine, the VM instance to the other compute sled; meansfor associating, by the compute engine, the region of memory in thememory pool with the other compute sled; and circuitry for starting-up,by the compute engine, the VM instance on the other compute sled.

Example 28 includes the subject matter of Example 27, and wherein thecircuitry for allocating the first set of resources of the compute sledcomprises means for determining a set of resources required by aworkload to be processed by the VM instance; and circuitry forallocating the first set of resources of the compute sled as a functionof the determined required set of resources.

Example 29 includes the subject matter of any of Examples 27 and 28, andwherein the circuitry for allocating the first set of resources of thecompute sled further comprises means for identifying available resourcesof each of the plurality of compute sleds; and circuitry for allocatingthe first set of resources of the compute sled as a function of theidentified available resources.

Example 30 includes the subject matter of any of Examples 27-29, andwherein the means for associating the region of memory in the memorypool of the memory sled with the compute sled comprises means fortransmitting a memory allocation request to a memory pool controller ofthe memory pool that is usable to allocate the region of memory and mapthe allocated region of memory to the compute sled.

Example 31 includes the subject matter of any of Examples 27-30, andwherein the circuitry for migrating the VM instance to the other computesled comprises circuitry for transmitting one or more threads associatedwith the workload associated with the VM instance to the other computesled.

Example 32 includes the subject matter of any of Examples 27-31, andwherein the means for associating the region of memory in the memorypool of the memory sled with the other compute sled comprises means fortransmitting a memory allocation request to a memory pool controller ofthe memory pool that is usable to map the allocated region of memory tothe other compute sled.

Example 33 includes the subject matter of any of Examples 27-32, andwherein the circuitry for allocating the second set of resources of thecompute sled comprises circuitry for retrieving a set of resourcesrequired by a workload being processed by the VM instance; and circuitryfor allocating the second set of resources of the compute sled as afunction of the retrieved required set of resources.

Example 34 includes the subject matter of any of Examples 27-33, andwherein the circuitry for allocating the second set of resources of theother compute sled further comprises means for identifying availableresources of each of the plurality of compute sleds; and circuitry forallocating the second set of resources of the other compute sled as afunction of the identified available resources.

1. A resource manager server for migrating virtual machines, theresource manager server comprising: a communication circuit; and acompute engine to: identify a compute sled of a plurality of computesleds for a virtual machine (VM) instance, wherein each of the computesleds is communicatively coupled to the resource manager server;allocate a first set of resources of the identified compute sled for theVM instance; associate a region of memory in a memory pool of a memorysled with the compute sled, wherein the memory sled is communicativelycoupled to the resource manager server; create the VM instance on thecompute sled; allocate, in response to determined determination that theVM instance is to be migrated, a second set of resources of anothercompute sled of the plurality of compute sleds for the VM instance;migrate the VM instance to the other compute sled; associate the regionof memory in the memory pool with the other compute sled; and start-upthe VM instance on the other compute sled.
 2. The resource managerserver of claim 1, wherein to allocate the first set of resources of thecompute sled comprises to (i) determine a set of resources required by aworkload to be processed by the VM instance and (ii) allocate the firstset of resources of the compute sled as a function of the determinedrequired set of resources.
 3. The resource manager server of claim 2,wherein to allocate the first set of resources of the compute sledfurther comprises to (i) identify available resources of each of theplurality of compute sleds and (ii) allocate the first set of resourcesof the compute sled as a function of the identified available resources.4. The resource manager server of claim 1, wherein to associate theregion of memory in the memory pool of the memory sled with the computesled comprises to transmit a memory allocation request to a memory poolcontroller of the memory pool that is usable to allocate the region ofmemory and map the allocated region of memory to the compute sled. 5.The resource manager server of claim 1, wherein to migrate the VMinstance to the other compute sled comprises to transmit one or morethreads associated with the workload associated with the VM instance tothe other compute sled.
 6. The resource manager server of claim 1,wherein to associate the region of memory in the memory pool of thememory sled with the other compute sled comprises to transmit a memoryallocation request to a memory pool controller of the memory pool thatis usable to map the allocated region of memory to the other computesled.
 7. The resource manager server of claim 1, wherein to allocate thesecond set of resources of the compute sled comprises to (i) retrieve aset of resources required by a workload being processed by the VMinstance and (ii) allocate the second set of resources of the computesled as a function of the retrieved required set of resources.
 8. Theresource manager server of claim 7, wherein to allocate the second setof resources of the other compute sled further comprises to (i) identifyavailable resources of each of the plurality of compute sleds and (ii)allocate the second set of resources of the other compute sled as afunction of the identified available resources.
 9. One or moremachine-readable storage media comprising a plurality of instructionsstored thereon that, in response to being executed, cause a resourcemanager server to: identify a compute sled of a plurality of computesleds for a virtual machine (VM) instance, wherein each of the computesleds is communicatively coupled to the resource manager server;allocate a first set of resources of the identified compute sled for theVM instance; associate a region of memory in a memory pool of a memorysled with the compute sled, wherein the memory sled is communicativelycoupled to the resource manager server; create the VM instance on thecompute sled; allocate, in response to determined determination that theVM instance is to be migrated, a second set of resources of anothercompute sled of the plurality of compute sleds for the VM instance;migrate the VM instance to the other compute sled; associate the regionof memory in the memory pool with the other compute sled; and start-upthe VM instance on the other compute sled.
 10. The one or moremachine-readable storage media of claim 9, wherein to allocate the firstset of resources of the compute sled comprises to (i) determine a set ofresources required by a workload to be processed by the VM instance and(ii) allocate the first set of resources of the compute sled as afunction of the determined required set of resources.
 11. The one ormore machine-readable storage media of claim 10, wherein to allocate thefirst set of resources of the compute sled further comprises to (i)identify available resources of each of the plurality of compute sledsand (ii) allocate the first set of resources of the compute sled as afunction of the identified available resources.
 12. The one or moremachine-readable storage media of claim 9, wherein to associate theregion of memory in the memory pool of the memory sled with the computesled comprises to transmit a memory allocation request to a memory poolcontroller of the memory pool that is usable to allocate the region ofmemory and map the allocated region of memory to the compute sled. 13.The one or more machine-readable storage media of claim 9, wherein tomigrate the VM instance to the other compute sled comprises to transmitone or more threads associated with the workload associated with the VMinstance to the other compute sled.
 14. The one or more machine-readablestorage media of claim 9, wherein to associate the region of memory inthe memory pool of the memory sled with the other compute sled comprisesto transmit a memory allocation request to a memory pool controller ofthe memory pool that is usable to map the allocated region of memory tothe other compute sled.
 15. The one or more machine-readable storagemedia of claim 9, wherein to allocate the second set of resources of thecompute sled comprises to (i) retrieve a set of resources required by aworkload being processed by the VM instance and (ii) allocate the secondset of resources of the compute sled as a function of the retrievedrequired set of resources.
 16. The one or more machine-readable storagemedia of claim 15, wherein to allocate the second set of resources ofthe other compute sled further comprises to (i) identify availableresources of each of the plurality of compute sleds and (ii) allocatethe second set of resources of the other compute sled as a function ofthe identified available resources.
 17. A resource manager server formigrating virtual machines, the resource manager server comprising:circuitry for identifying, by a compute engine of the resource managerserver, a compute sled of a plurality of compute sleds for a virtualmachine (VM) instance, wherein each of the compute sleds iscommunicatively coupled to the resource manager server; circuitry forallocating, by the compute engine, a first set of resources of theidentified compute sled for the VM instance; means for associating, bythe compute engine, a region of memory in a memory pool of a memory sledwith the compute sled, wherein the memory sled is communicativelycoupled to the resource manager server; circuitry for creating, by thecompute engine, the VM instance on the compute sled; circuitry forallocating, by the compute engine and in response to determineddetermination that the VM instance is to be migrated, a second set ofresources of another compute sled of the plurality of compute sleds forthe VM instance; circuitry for migrating, by the compute engine, the VMinstance to the other compute sled; means for associating, by thecompute engine, the region of memory in the memory pool with the othercompute sled; and circuitry for starting-up, by the compute engine, theVM instance on the other compute sled.
 18. The resource manager serverof claim 17, wherein the circuitry for allocating the first set ofresources of the compute sled comprises: means for determining a set ofresources required by a workload to be processed by the VM instance; andcircuitry for allocating the first set of resources of the compute sledas a function of the determined required set of resources.
 19. Theresource manager server of claim 18, wherein the circuitry forallocating the first set of resources of the compute sled furthercomprises: means for identifying available resources of each of theplurality of compute sleds; and circuitry for allocating the first setof resources of the compute sled as a function of the identifiedavailable resources.
 20. The resource manager server of claim 17,wherein the means for associating the region of memory in the memorypool of the memory sled with the compute sled comprises means fortransmitting a memory allocation request to a memory pool controller ofthe memory pool that is usable to allocate the region of memory and mapthe allocated region of memory to the compute sled.
 21. The resourcemanager server of claim 17, wherein the circuitry for migrating the VMinstance to the other compute sled comprises circuitry for transmittingone or more threads associated with the workload associated with the VMinstance to the other compute sled.
 22. The resource manager server ofclaim 17, wherein the means for associating the region of memory in thememory pool of the memory sled with the other compute sled comprisesmeans for transmitting a memory allocation request to a memory poolcontroller of the memory pool that is usable to map the allocated regionof memory to the other compute sled.
 23. The resource manager server ofclaim 17, wherein the circuitry for allocating the second set ofresources of the compute sled comprises: circuitry for retrieving a setof resources required by a workload being processed by the VM instance;and circuitry for allocating the second set of resources of the computesled as a function of the retrieved required set of resources.
 24. Theresource manager server of claim 23, wherein the circuitry forallocating the second set of resources of the other compute sled furthercomprises: means for identifying available resources of each of theplurality of compute sleds; and circuitry for allocating the second setof resources of the other compute sled as a function of the identifiedavailable resources.